Wireless SoC Design Engineer
Apple Inc., San Francisco, CA, United States
Team Overview Come and join Apple’s growing wireless silicon development team. The wireless SoC organization handles all aspects of wireless silicon development, emphasizing highly energy‑efficient design and new technologies that transform the user experience at the product level. The team spans RF/analog architecture, systems/PHY/MAC architecture, VLSI/RTL design, emulation, design verification, test, validation, and firmware/software engineering.
Description In this role you will design CPU‑based subsystems for high‑performance, low‑power wireless SoCs. You will work closely with SoC architects and IP developers to meet power, performance, and area goals, with a focus on low‑power metrics. You will participate in hardware/software/power partitioning discussions with software, firmware, and platform engineering teams and integrate industry‑standard and custom hardware IPs into SoCs.
Responsibilities Writing micro‑architecture and design specifications.
Coding design in SystemVerilog following established design guidelines, owning all aspects of RTL development.
Integrating IP blocks and optimizing memories/hard macros for the block.
Supporting verification efforts at multiple levels.
Checking designs with industry‑standard static tools such as LINT, CDC, and RDC.
Analyzing and optimizing area, timing, and power.
Collaborating with multidisciplinary groups to deliver designs on time and with the highest quality, incorporating proper checks at every stage of the design process.
Minimum Qualifications Bachelor’s degree.
Preferred Qualifications Familiarity with the ASIC design flow.
Knowledge of digital design, SoC architecture, and HDL languages such as Verilog.
Experience writing micro‑architecture specifications and converting them to design.
Exposure to design methodologies and industry‑standard EDA tools.
Experience with AXI/AHB bus fabric and processor subsystems.
Understanding of UPF and low‑power design & implementation techniques.
Self‑starter and willingness to learn.
Compensation and Benefits Base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $126,800 and $220,900, based on skills, qualifications, experience, and location.
Apple employees can become shareholders through discretionary employee stock programs, receive a discounted stock purchase plan, and are eligible for discretionary restricted stock unit awards. Additional benefits include comprehensive medical and dental coverage, retirement benefits, discounted products and free services, and education reimbursement for tuition. This role may also be eligible for discretionary bonuses, commission payments, and relocation assistance.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
EEO Statement Apple is an equal‑opportunity employer committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
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Description In this role you will design CPU‑based subsystems for high‑performance, low‑power wireless SoCs. You will work closely with SoC architects and IP developers to meet power, performance, and area goals, with a focus on low‑power metrics. You will participate in hardware/software/power partitioning discussions with software, firmware, and platform engineering teams and integrate industry‑standard and custom hardware IPs into SoCs.
Responsibilities Writing micro‑architecture and design specifications.
Coding design in SystemVerilog following established design guidelines, owning all aspects of RTL development.
Integrating IP blocks and optimizing memories/hard macros for the block.
Supporting verification efforts at multiple levels.
Checking designs with industry‑standard static tools such as LINT, CDC, and RDC.
Analyzing and optimizing area, timing, and power.
Collaborating with multidisciplinary groups to deliver designs on time and with the highest quality, incorporating proper checks at every stage of the design process.
Minimum Qualifications Bachelor’s degree.
Preferred Qualifications Familiarity with the ASIC design flow.
Knowledge of digital design, SoC architecture, and HDL languages such as Verilog.
Experience writing micro‑architecture specifications and converting them to design.
Exposure to design methodologies and industry‑standard EDA tools.
Experience with AXI/AHB bus fabric and processor subsystems.
Understanding of UPF and low‑power design & implementation techniques.
Self‑starter and willingness to learn.
Compensation and Benefits Base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $126,800 and $220,900, based on skills, qualifications, experience, and location.
Apple employees can become shareholders through discretionary employee stock programs, receive a discounted stock purchase plan, and are eligible for discretionary restricted stock unit awards. Additional benefits include comprehensive medical and dental coverage, retirement benefits, discounted products and free services, and education reimbursement for tuition. This role may also be eligible for discretionary bonuses, commission payments, and relocation assistance.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
EEO Statement Apple is an equal‑opportunity employer committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
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