SerDes RTL Design Engineer for High-Speed PHY

A leading technology company is seeking an innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in advanced CMOS processes. This role emphasizes collaboration with system architects and requires proficiency in RTL design using Verilog/System Verilog. Ideal candidates possess strong problem-solving skills, are committed to innovation, and hold a degree in electrical or computer engineering. This role is based in San Jose, CA, with a focus on digital design and verification responsibilities. Visa sponsorship is not offered.
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