RTL Design Sr Staff Engineer in Ho Chi Minh city
Synopsys, Inc., Sunnyvale, CA, United States
Alternate Job Titles:
Staff RTL Design Engineer
Senior Digital Design Engineer
ASIC RTL Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are an experienced RTL designer eager to lead, innovate, and collaborate. You bring strong technical skills and a passion for high-speed memory and interface solutions. You excel at problem-solving, clear communication, and thrive in a team environment. Your experience covers the full silicon development flow, and you’re excited to make a tangible impact on advanced test chip projects.
What You’ll Be Doing:
Designing and verifying DDRPHY/LPDDRR/HBM test chips using SystemVerilog/Verilog.
Collaborating with analog and mixed-signal teams.
Automating workflows with scripting languages.
Debugging complex hardware issues in lab bring-up and validation.
Documenting specifications and processes.
Driving improvements in design and DFT/DFM flows.
The Impact You Will Have:
Delivering reliable, high-speed memory IP for next-gen platforms.
Supporting rapid customer time-to-market.
Enhancing testchip team capabilities and innovation.
Mentoring and sharing expertise with peers.
Ensuring product quality through robust verification.
Promoting a collaborative, learning-focused culture.
What You’ll Need:
6+ years in RTL design/verification (SystemVerilog/Verilog).
Experience with high-speed interfaces (DDR/HBM preferred).
Skill in scripting (Python, Perl, Tcl, Shell).
Knowledge of ASIC/IP flows and DFT/DFM.
Experience debugging complex hardware issues.
Who You Are:
Clear communicator and team player.
Analytical, proactive, and adaptable.
Open to learning and mentoring.
The Team You’ll Be A Part Of:
Join our expert testchip team in Ho Chi Minh City, collaborating across digital, analog, and mixed-signal domains to deliver industry-leading memory interface solutions.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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Staff RTL Design Engineer
Senior Digital Design Engineer
ASIC RTL Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are an experienced RTL designer eager to lead, innovate, and collaborate. You bring strong technical skills and a passion for high-speed memory and interface solutions. You excel at problem-solving, clear communication, and thrive in a team environment. Your experience covers the full silicon development flow, and you’re excited to make a tangible impact on advanced test chip projects.
What You’ll Be Doing:
Designing and verifying DDRPHY/LPDDRR/HBM test chips using SystemVerilog/Verilog.
Collaborating with analog and mixed-signal teams.
Automating workflows with scripting languages.
Debugging complex hardware issues in lab bring-up and validation.
Documenting specifications and processes.
Driving improvements in design and DFT/DFM flows.
The Impact You Will Have:
Delivering reliable, high-speed memory IP for next-gen platforms.
Supporting rapid customer time-to-market.
Enhancing testchip team capabilities and innovation.
Mentoring and sharing expertise with peers.
Ensuring product quality through robust verification.
Promoting a collaborative, learning-focused culture.
What You’ll Need:
6+ years in RTL design/verification (SystemVerilog/Verilog).
Experience with high-speed interfaces (DDR/HBM preferred).
Skill in scripting (Python, Perl, Tcl, Shell).
Knowledge of ASIC/IP flows and DFT/DFM.
Experience debugging complex hardware issues.
Who You Are:
Clear communicator and team player.
Analytical, proactive, and adaptable.
Open to learning and mentoring.
The Team You’ll Be A Part Of:
Join our expert testchip team in Ho Chi Minh City, collaborating across digital, analog, and mixed-signal domains to deliver industry-leading memory interface solutions.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
#J-18808-Ljbffr