Senior NPU Architect (San Jose)

About the Role
We are seeking a

Senior NPU Architect

to define the architecture of next-generation AI accelerators for high-performance and power-efficient autonomous driving NPU. You will drive architecture decisions across compute, memory hierarchy, interconnect, dataflow, and software co-design, enabling competitive performance for modern AI workloads such as CNNs, Transformers, multimodal models, and LLM inference.

Key Responsibilities
Define NPU architecture and key design directions for compute, memory, interconnect, and execution model.
Analyze AI workloads and translate them into architecture requirements and trade-offs.
Drive architecture modeling, bottleneck analysis, and architecture exploration.
Partner with compiler, runtime, and algorithm teams on hardware/software co-design.
Guide architectural optimization for performance, power, area, and scalability.
Work with RTL, verification, and software teams to ensure successful implementation.

Qualifications
MS or PhD in EE, CE, CS, or related field.
8+ years of experience in NPU, GPU, CPU, ASIC, or computer architecture.
Strong understanding of AI/ML workloads, memory systems, parallel processing, and performance optimization.
Proven experience in architecture definition, modeling, and hardware/software co-design.
Familiarity with low-precision computing and quantization, such as INT8, FP16, BF16, or FP8.
Strong technical leadership and cross-functional communication skills.
Preferred Qualifications
Experience with AI accelerators for edge AI, datacenter AI, or autonomous driving.
Familiarity with AI compiler/runtime stacks and workload mapping.
Track record of architectural innovation, silicon delivery, or published technical contributions.