Senior Power and Performance Engineer - System Memory
NVIDIA, Austin, TX, United States
NVIDIA Silicon Solutions Group seeks a hardworking engineer to join a silicon HW team. As a team member, you will develop and validate system-level features with a deep understanding of product needs that will be delivered to notebook, desktop, embedded, automotive, and professional solution markets. Prior experience in the lab with system-level post-silicon bring-up and debug is highly desired.
Responsibilities
Build roadmaps of memory system-level features to address low power, low noise, perf/watt efficient, and stable/reliable product needs by doing prototyping, use case analysis, and system-level cost/benefit tradeoff.
Architect, design, and integrate memory system-level features, controllers, and policies - including binning, pairing, and adaptive control techniques based on the roadmap to optimize product performance, power, and reliability/stability.
Collaborate with architecture, ASIC, board/platform design, software/firmware, marketing, and other multi-functional teams to drive architecture, design, and debug.
Expand power improvement initiatives to cover various products and market segments, including high-demand environments such as data centers. Drive scalable, power-efficient, and reliable memory system solutions across diverse platforms.
Keep track of the latest industry direction, market needs, and technology development; incorporate them into future roadmaps to build more competitive products.
Lead debug, craft WARs, and support bringup, validation, manufacturing, and customer issues on relevant features.
Qualifications
BS or MS degree in EE/CE or equivalent experience.
8+ years of experience in memory subsystem architecture, design, and validation, with a strong focus on system-level features that optimize memory power for perf-per-watt efficiency in datacenter or high-perf systems.
Strong fundamentals in EE, digital/analog design, signal integrity, low power design, memory power management techniques, timing analysis, and architecture.
It is crucial to have a deep understanding of how system-level memory interacts with different IPs and SW/FW, including their impact on power, latency, and reliability.
Experience with control systems, boot/reset flows, and memory controller micro-architecture.
Validated hands‑on lab experience with silicon bringup, lab debug, and lab tools (oscilloscopes, multimeters, logic analyzers).
Excellent problem‑solving, teamwork, and interpersonal skills.
Experience with Python, Perl, C/C++, Windows, and Linux is a plus.
Benefits
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal‑opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Responsibilities
Build roadmaps of memory system-level features to address low power, low noise, perf/watt efficient, and stable/reliable product needs by doing prototyping, use case analysis, and system-level cost/benefit tradeoff.
Architect, design, and integrate memory system-level features, controllers, and policies - including binning, pairing, and adaptive control techniques based on the roadmap to optimize product performance, power, and reliability/stability.
Collaborate with architecture, ASIC, board/platform design, software/firmware, marketing, and other multi-functional teams to drive architecture, design, and debug.
Expand power improvement initiatives to cover various products and market segments, including high-demand environments such as data centers. Drive scalable, power-efficient, and reliable memory system solutions across diverse platforms.
Keep track of the latest industry direction, market needs, and technology development; incorporate them into future roadmaps to build more competitive products.
Lead debug, craft WARs, and support bringup, validation, manufacturing, and customer issues on relevant features.
Qualifications
BS or MS degree in EE/CE or equivalent experience.
8+ years of experience in memory subsystem architecture, design, and validation, with a strong focus on system-level features that optimize memory power for perf-per-watt efficiency in datacenter or high-perf systems.
Strong fundamentals in EE, digital/analog design, signal integrity, low power design, memory power management techniques, timing analysis, and architecture.
It is crucial to have a deep understanding of how system-level memory interacts with different IPs and SW/FW, including their impact on power, latency, and reliability.
Experience with control systems, boot/reset flows, and memory controller micro-architecture.
Validated hands‑on lab experience with silicon bringup, lab debug, and lab tools (oscilloscopes, multimeters, logic analyzers).
Excellent problem‑solving, teamwork, and interpersonal skills.
Experience with Python, Perl, C/C++, Windows, and Linux is a plus.
Benefits
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal‑opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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