Principal SoC DFT Engineer, HBM
Micron Technology, Folsom, CA, United States
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Principal SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chip (SoC) designs. This role is part of the SoC execution team, working closely with RTL design, verification, physical design, and product engineering to ensure robust, scalable, and manufacturable test solutions from pre-silicon development through tapeout and product bring‑up.
Responsibilities
Own SoC-level DFT implementation, including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base‑die designs.
Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints.
Implement and integrate DFT logic at the block, subsystem, and full‑chip levels, working closely with RTL and integration teams.
Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff.
Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability and smooth silicon bring‑up.
Support pre‑silicon debug of DFT‑related issues and assist with post‑silicon bring‑up and yield/debug analysis.
Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs.
Required Experience
Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field.
7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.
Job title and level can scale depending on experience and qualifications.
Preferred Qualifications
Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design.
Experience working with large, complex SoCs involving multiple IPs and subsystems.
Proficiency with industry‑standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation.
Compensation
US base salary range: $146,000 – $309,000 per year.
Additional compensation may include benefits, bonuses and equity.
Benefits
Medical, dental and vision coverage.
Paid time off and paid holidays.
Paid family leave.
Income protection if unable to work due to illness or injury.
Robust paid time‑off program and paid holidays.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
#J-18808-Ljbffr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Principal SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chip (SoC) designs. This role is part of the SoC execution team, working closely with RTL design, verification, physical design, and product engineering to ensure robust, scalable, and manufacturable test solutions from pre-silicon development through tapeout and product bring‑up.
Responsibilities
Own SoC-level DFT implementation, including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base‑die designs.
Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints.
Implement and integrate DFT logic at the block, subsystem, and full‑chip levels, working closely with RTL and integration teams.
Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff.
Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability and smooth silicon bring‑up.
Support pre‑silicon debug of DFT‑related issues and assist with post‑silicon bring‑up and yield/debug analysis.
Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs.
Required Experience
Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field.
7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.
Job title and level can scale depending on experience and qualifications.
Preferred Qualifications
Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design.
Experience working with large, complex SoCs involving multiple IPs and subsystems.
Proficiency with industry‑standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation.
Compensation
US base salary range: $146,000 – $309,000 per year.
Additional compensation may include benefits, bonuses and equity.
Benefits
Medical, dental and vision coverage.
Paid time off and paid holidays.
Paid family leave.
Income protection if unable to work due to illness or injury.
Robust paid time‑off program and paid holidays.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
#J-18808-Ljbffr