Senior DFT ATPG Engineer – Hybrid, RTL/DFT Innovation

Intel Corporation is searching for an Experienced DFT ATPG Engineer in Santa Clara, California. This role involves developing logic design, RTL coding, and collaborating on DFT architecture and features. Candidates should have a BS or MS in EE/CE with DFT experience. The position offers a hybrid work model, competitive pay, and opportunities for professional growth in a dynamic environment focused on cutting-edge semiconductor technologies.
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