ASIC Digital Design, Sr Manager
Synopsys, Inc., Sunnyvale, CA, United States
ASIC Digital Design, Sr Manager
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to help transform the future through continuous technological innovation.
You Are:
You are an experienced
ASIC Digital Design Manager
with strong hands‑on expertise in PCIe digital design and architecture, capable of leading a team while remaining deeply engaged in technical execution. You bring extensive experience defining and implementing
RTL and micro‑architecture for complex, high‑speed interface IP , combined with proven team‑lead and people‑management skills.
You setting technical direction with your team, making architectural trade‑offs, and driving design decisions for current and next‑generation PCIe IP. You are comfortable working directly with RTL, reviewing detailed design implementations, and guiding engineers through complex debug and convergence challenges. Your background includes exposure to adjacent interconnect technologies such as
CXL, AMBA, DDR, UCIe .
As a experienced leader, you foster a culture of accountability, collaboration, and technical excellence. You mentor engineers through hands‑on guidance and design reviews, communicate clearly across disciplines, and work closely with cross‑functional teams to deliver
high‑quality, silicon‑proven PCIe IP
for commercial, enterprise, and automotive applications.
What You’ll Be Doing:
Leading and managing a
team of ASIC digital design engineers , providing day‑to‑day technical guidance, mentoring, and performance management.
Owning
PCIe digital architecture and RTL design execution , remaining hands‑on while leading design efforts at block, subsystem, and IP‑integration levels.
Defining
micro‑architecture, design specifications, and implementation approaches
for high‑performance, power‑efficient, and scalable PCIe designs.
Leading end‑to‑end digital design activities, including
architecture definition, RTL development, debug, design convergence, and post‑silicon support .
Serving as the
PCIe technical architect
for the team, guiding key design decisions and resolving complex technical issues.
Planning and prioritizing design work,
balancing hands‑on technical involvement with team execution, schedules, and resource needs .
Driving
design quality
through rigorous design reviews, coding standards, and RTL maintainability practices .
Collaborating closely with
verification, physical design, formal, emulation, firmware and system teams
to ensure smooth IP integration and silicon success.
Coaching and developing engineers through
hands‑on technical mentoring , design feedback, and career development discussions.
Promoting a culture of
technical ownership, accountability, and continuous improvement
within the team.
Identifying opportunities to improve
AI‑driven design methodologies, workflows, and productivity , while keeping focus on design execution.
Communicating design status, technical risks, and trade‑offs effectively to senior management and cross‑functional stakeholders.
The Impact You Will Have:
Deliver
industry‑leading PCIe digital IP
with high performance, robustness, and scalability.
Drive strong architectural and design execution for PCIe cores used by leading customers.
Improve design quality, predictability, and execution efficiency through strong technical leadership.
Build and lead a
highly capable ASIC digital design team
with deep PCIe expertise.
Strengthen Synopsys’ position as a leader in high‑speed interface IP across commercial, enterprise, and automotive markets.
What You’ll Need:
Bachelor’s degree in Electrical Engineering (BSEE) with 12+ years of experience, or Master’s degree (MSEE) with 10+ years.
Demonstrated experience as a
team lead or people manager
in an ASIC digital design environment.
Extensive hands‑on ASIC RTL design experience, with direct ownership of complex digital designs.
Deep expertise in
PCIe digital design and architecture ; experience with
CXL, DDR, AMBA, UCIe
or related protocols is highly desirable.
Strong understanding of ASIC design fundamentals including clocking, resets, low‑power techniques, and design for test .
Proven ability to define
PCIe micro‑architecture
and drive designs from concept through silicon.
Experience with
AI‑driven tools, flows and methodologies . Familiarity with scripting languages (Perl, TCL, Python) for design automation is a plus.
Who You Are:
Demonstrated experience as a
team lead or people manager
in an ASIC digital design environment.
A
hands‑on PCIe architect
who enjoys leading by technical example.
Comfortable balancing design execution with team leadership responsibilities.
A clear communicator who works effectively across engineering disciplines.
A collaborative leader who values quality, ownership, and knowledge sharing.
The Team You’ll Be A Part Of:
You will join the
DesignWare Digital IP R&D organization
at Synopsys, focused on architecting and delivering world‑class PCIe IP. The team spans multiple global sites and works closely with verification, analog, system, and platform teams to deliver silicon‑proven solutions for next‑generation semiconductor products.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits designed to support you and your family. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will share specific details on compensation and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
#J-18808-Ljbffr
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to help transform the future through continuous technological innovation.
You Are:
You are an experienced
ASIC Digital Design Manager
with strong hands‑on expertise in PCIe digital design and architecture, capable of leading a team while remaining deeply engaged in technical execution. You bring extensive experience defining and implementing
RTL and micro‑architecture for complex, high‑speed interface IP , combined with proven team‑lead and people‑management skills.
You setting technical direction with your team, making architectural trade‑offs, and driving design decisions for current and next‑generation PCIe IP. You are comfortable working directly with RTL, reviewing detailed design implementations, and guiding engineers through complex debug and convergence challenges. Your background includes exposure to adjacent interconnect technologies such as
CXL, AMBA, DDR, UCIe .
As a experienced leader, you foster a culture of accountability, collaboration, and technical excellence. You mentor engineers through hands‑on guidance and design reviews, communicate clearly across disciplines, and work closely with cross‑functional teams to deliver
high‑quality, silicon‑proven PCIe IP
for commercial, enterprise, and automotive applications.
What You’ll Be Doing:
Leading and managing a
team of ASIC digital design engineers , providing day‑to‑day technical guidance, mentoring, and performance management.
Owning
PCIe digital architecture and RTL design execution , remaining hands‑on while leading design efforts at block, subsystem, and IP‑integration levels.
Defining
micro‑architecture, design specifications, and implementation approaches
for high‑performance, power‑efficient, and scalable PCIe designs.
Leading end‑to‑end digital design activities, including
architecture definition, RTL development, debug, design convergence, and post‑silicon support .
Serving as the
PCIe technical architect
for the team, guiding key design decisions and resolving complex technical issues.
Planning and prioritizing design work,
balancing hands‑on technical involvement with team execution, schedules, and resource needs .
Driving
design quality
through rigorous design reviews, coding standards, and RTL maintainability practices .
Collaborating closely with
verification, physical design, formal, emulation, firmware and system teams
to ensure smooth IP integration and silicon success.
Coaching and developing engineers through
hands‑on technical mentoring , design feedback, and career development discussions.
Promoting a culture of
technical ownership, accountability, and continuous improvement
within the team.
Identifying opportunities to improve
AI‑driven design methodologies, workflows, and productivity , while keeping focus on design execution.
Communicating design status, technical risks, and trade‑offs effectively to senior management and cross‑functional stakeholders.
The Impact You Will Have:
Deliver
industry‑leading PCIe digital IP
with high performance, robustness, and scalability.
Drive strong architectural and design execution for PCIe cores used by leading customers.
Improve design quality, predictability, and execution efficiency through strong technical leadership.
Build and lead a
highly capable ASIC digital design team
with deep PCIe expertise.
Strengthen Synopsys’ position as a leader in high‑speed interface IP across commercial, enterprise, and automotive markets.
What You’ll Need:
Bachelor’s degree in Electrical Engineering (BSEE) with 12+ years of experience, or Master’s degree (MSEE) with 10+ years.
Demonstrated experience as a
team lead or people manager
in an ASIC digital design environment.
Extensive hands‑on ASIC RTL design experience, with direct ownership of complex digital designs.
Deep expertise in
PCIe digital design and architecture ; experience with
CXL, DDR, AMBA, UCIe
or related protocols is highly desirable.
Strong understanding of ASIC design fundamentals including clocking, resets, low‑power techniques, and design for test .
Proven ability to define
PCIe micro‑architecture
and drive designs from concept through silicon.
Experience with
AI‑driven tools, flows and methodologies . Familiarity with scripting languages (Perl, TCL, Python) for design automation is a plus.
Who You Are:
Demonstrated experience as a
team lead or people manager
in an ASIC digital design environment.
A
hands‑on PCIe architect
who enjoys leading by technical example.
Comfortable balancing design execution with team leadership responsibilities.
A clear communicator who works effectively across engineering disciplines.
A collaborative leader who values quality, ownership, and knowledge sharing.
The Team You’ll Be A Part Of:
You will join the
DesignWare Digital IP R&D organization
at Synopsys, focused on architecting and delivering world‑class PCIe IP. The team spans multiple global sites and works closely with verification, analog, system, and platform teams to deliver silicon‑proven solutions for next‑generation semiconductor products.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits designed to support you and your family. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will share specific details on compensation and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
#J-18808-Ljbffr