Senior R&D Engineer, C/C++ & Timing Constraint Tech

Synopsys, Inc. is seeking an experienced engineer to drive innovations in timing constraint management. This role involves designing algorithms for high-performance chip design, collaborating within a skilled engineering team to enhance EDA products. The ideal candidate has at least 8 years of experience in software engineering and algorithm development, with strong skills in C/C++ and scripting languages. Join us to contribute to cutting-edge design methodologies and empower customers in achieving optimal results in chip design flows.
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