Senior ASIC Physical Design Lead (RTL-GDSII)

Synopsys, Inc. in Sunnyvale, California, is seeking a highly motivated individual with extensive experience in physical design for complex Mixed Signal IPs. The role requires strong knowledge of the design cycle from RTL to GDSII, along with advanced PnR skills. Responsibilities include leading the implementation of high-speed interface IPs and collaborating with cross-functional teams to ensure design success. Synopsys offers a range of health and wellness benefits and supports continuous improvement and innovation in technology.
#J-18808-Ljbffr