High speed Board Design Engineer
Pyramid Consulting, Inc, San Jose, CA, United States
Immediate need for a talented
High speed
Board Design Engineer.
This is a
06-12+ months contract
opportunity with long-term potential and is location in
San Jose, CA/ Sunnyvale, CA(Onsite).
Please review the job description below and contact me ASAP if you are interested.
Job Diva ID: 26-12621
Pay Range: $45 - $50/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
Key Responsibilities :
Schematic development in
Concept HDL (Cadence Allegro v23.1+)
High‑speed and memory interface design and debug
Board bring‑up using advanced lab equipment
FPGA board design and validation
Key Requirements and Technology Experience:
7–12 years high‑speed board design experience
Cadence Allegro v23.1+
Concept HDL
Signal Integrity analysis
DDR3 / DDR4 / DDR5, LPDDR4 / LPDDR5
Intel / high‑end SoC designs
High‑complexity FPGA boards (Agilex preferred)
Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
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High speed
Board Design Engineer.
This is a
06-12+ months contract
opportunity with long-term potential and is location in
San Jose, CA/ Sunnyvale, CA(Onsite).
Please review the job description below and contact me ASAP if you are interested.
Job Diva ID: 26-12621
Pay Range: $45 - $50/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
Key Responsibilities :
Schematic development in
Concept HDL (Cadence Allegro v23.1+)
High‑speed and memory interface design and debug
Board bring‑up using advanced lab equipment
FPGA board design and validation
Key Requirements and Technology Experience:
7–12 years high‑speed board design experience
Cadence Allegro v23.1+
Concept HDL
Signal Integrity analysis
DDR3 / DDR4 / DDR5, LPDDR4 / LPDDR5
Intel / high‑end SoC designs
High‑complexity FPGA boards (Agilex preferred)
Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
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