Principal Mixed Signal Architect
Blue Origin, Seattle, WA, United States
We are seeking a
Principal Mixed-Signal Architect
to lead the definition and development of high-performance mixed-signal subsystems for advanced communication and data-conversion SoCs. This role will own architecture, top-level specifications, behavioral modeling, IP strategy, and cross-functional integration for critical mixed-signal building blocks such as
SerDes, ADCs, PLLs, VGAs, TIAs, and quantizers .
This role is open to Seattle, Bay, San Diego and Austin Areas. Relocation provided. Travel expected up to 15% of the time.
Responsibilities
Own top-level specifications for mixed-signal subsystems, including link budgets for SerDes (PAM4/NRZ) and ENOB/SNDR targets for high-speed ADCs.
Develop high-level behavioral models in MATLAB, Simulink, or SystemVerilog-AMS to validate system performance before circuit implementation.
Evaluate make-versus-buy decisions for SerDes and ADC IP and recommend the best technical and business path.
For internally developed solutions, lead circuit architecture and design implementation of key analog/mixed-signal blocks such as PLLs, VGAs, TIAs, and quantizers.
Define calibration and adaptation algorithms, including FFE, DFE, and adaptive gain control, that are implemented in RTL and used to optimize analog block performance.
Partner with packaging and physical design teams to define pinouts, bump maps, guard rings, and isolation strategies that minimize noise coupling between high-speed analog and noisy digital logic.
Drive cross-functional architecture tradeoffs across analog, digital, packaging, and system teams.
Lead post-silicon validation of mixed-signal subsystems in the lab using high-speed test equipment such as oscilloscopes and BERTs.
Support debug, characterization, and performance correlation between simulation and silicon results.
Provide technical leadership and mentorship across mixed-signal architecture and design activities.
Basic Qualifications
Bachelor of Sciences Degree in Electrical Engineering with a focus on Analog/Mixed-Signal design.
15+ years of experience in mixed-signal IC design.
Proven track record delivering high-speed SerDes (16G/32G/56G/112G) and high-speed ADCs such as SAR, Pipeline, or Sigma-Delta architectures.
Deep experience in advanced FinFET process nodes (7nm, 5nm, or below).
Strong expertise managing layout-dependent effects (LDE), electromigration, and other advanced-node implementation challenges.
Expert knowledge of industry-standard design and simulation tools including Cadence Virtuoso, Spectre/HSPICE, and AMS Designer.
Strong understanding of mixed-signal system architecture, performance tradeoffs, and silicon validation.
Experience working across architecture, circuit design, RTL, packaging, and lab validation teams.
Preferred Qualifications
MS or PhD in Electrical Engineering with a focus on Analog/Mixed-Signal design.
Familiarity with EM simulation tools such as EMX or Ansys.
Understanding of high-speed interface and networking protocols such as PCIe Gen5/Gen6 and Ethernet.
Experience defining calibration, adaptation, and equalization schemes for high-speed links and data converters.
Background in system modeling and architecture evaluation for communication or sensor-interface applications.
Experience partnering with packaging teams on signal integrity, substrate noise, and high-speed integration challenges.
Strong lab bring-up and post-silicon debug experience for mixed-signal silicon.
Compensation Range for CA applicants: $230,773.00 - $323,081.85. For WA applicants: $230,773.00 - $323,081.85. Other site ranges may differ.
Benefits
Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match up to 5%, and an Education Support Program.
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.
Equal Employment Opportunity
Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated work force. Blue Origin hires and promotes people on the basis of their qualifications, performance, and abilities. We support the establishment and maintenance of a workplace that fosters trust, equality, and teamwork. We provide all qualified applicants for employment and employees with equal opportunities for hire, promotion, and other terms and conditions of employment, regardless of their race, color, religion, sex, sexual orientation, gender identity, national origin/ethnicity, age, physical or mental disability, genetic factors, military/veteran status, or any other status or characteristic protected by federal, state, and/or local law.
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Principal Mixed-Signal Architect
to lead the definition and development of high-performance mixed-signal subsystems for advanced communication and data-conversion SoCs. This role will own architecture, top-level specifications, behavioral modeling, IP strategy, and cross-functional integration for critical mixed-signal building blocks such as
SerDes, ADCs, PLLs, VGAs, TIAs, and quantizers .
This role is open to Seattle, Bay, San Diego and Austin Areas. Relocation provided. Travel expected up to 15% of the time.
Responsibilities
Own top-level specifications for mixed-signal subsystems, including link budgets for SerDes (PAM4/NRZ) and ENOB/SNDR targets for high-speed ADCs.
Develop high-level behavioral models in MATLAB, Simulink, or SystemVerilog-AMS to validate system performance before circuit implementation.
Evaluate make-versus-buy decisions for SerDes and ADC IP and recommend the best technical and business path.
For internally developed solutions, lead circuit architecture and design implementation of key analog/mixed-signal blocks such as PLLs, VGAs, TIAs, and quantizers.
Define calibration and adaptation algorithms, including FFE, DFE, and adaptive gain control, that are implemented in RTL and used to optimize analog block performance.
Partner with packaging and physical design teams to define pinouts, bump maps, guard rings, and isolation strategies that minimize noise coupling between high-speed analog and noisy digital logic.
Drive cross-functional architecture tradeoffs across analog, digital, packaging, and system teams.
Lead post-silicon validation of mixed-signal subsystems in the lab using high-speed test equipment such as oscilloscopes and BERTs.
Support debug, characterization, and performance correlation between simulation and silicon results.
Provide technical leadership and mentorship across mixed-signal architecture and design activities.
Basic Qualifications
Bachelor of Sciences Degree in Electrical Engineering with a focus on Analog/Mixed-Signal design.
15+ years of experience in mixed-signal IC design.
Proven track record delivering high-speed SerDes (16G/32G/56G/112G) and high-speed ADCs such as SAR, Pipeline, or Sigma-Delta architectures.
Deep experience in advanced FinFET process nodes (7nm, 5nm, or below).
Strong expertise managing layout-dependent effects (LDE), electromigration, and other advanced-node implementation challenges.
Expert knowledge of industry-standard design and simulation tools including Cadence Virtuoso, Spectre/HSPICE, and AMS Designer.
Strong understanding of mixed-signal system architecture, performance tradeoffs, and silicon validation.
Experience working across architecture, circuit design, RTL, packaging, and lab validation teams.
Preferred Qualifications
MS or PhD in Electrical Engineering with a focus on Analog/Mixed-Signal design.
Familiarity with EM simulation tools such as EMX or Ansys.
Understanding of high-speed interface and networking protocols such as PCIe Gen5/Gen6 and Ethernet.
Experience defining calibration, adaptation, and equalization schemes for high-speed links and data converters.
Background in system modeling and architecture evaluation for communication or sensor-interface applications.
Experience partnering with packaging teams on signal integrity, substrate noise, and high-speed integration challenges.
Strong lab bring-up and post-silicon debug experience for mixed-signal silicon.
Compensation Range for CA applicants: $230,773.00 - $323,081.85. For WA applicants: $230,773.00 - $323,081.85. Other site ranges may differ.
Benefits
Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match up to 5%, and an Education Support Program.
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.
Equal Employment Opportunity
Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated work force. Blue Origin hires and promotes people on the basis of their qualifications, performance, and abilities. We support the establishment and maintenance of a workplace that fosters trust, equality, and teamwork. We provide all qualified applicants for employment and employees with equal opportunities for hire, promotion, and other terms and conditions of employment, regardless of their race, color, religion, sex, sexual orientation, gender identity, national origin/ethnicity, age, physical or mental disability, genetic factors, military/veteran status, or any other status or characteristic protected by federal, state, and/or local law.
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