SoC Floorplan Engineer — Hybrid, High‑Impact ASIC Layout

Intel is seeking a Physical Design Floorplanning Engineer to join our team in Boxborough, Massachusetts. In this role, you will be responsible for SoC floorplan activities, collaborating with various stakeholders, and enhancing methodologies and tools for floorplan design. The position requires a Bachelor's with 4+ years or a Master's with 3+ years of experience in electrical engineering and proficiency in EDA tools and programming languages. This role offers a hybrid work model and a competitive salary range from $141,910 to $269,100 USD annually.
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