Principal Engineer – Advanced IC Packaging
PowerLattice Technologies Inc, Phoenix, AZ, United States
About Us
Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.
About the Role
We’re a fast-moving startup building the foundation for next-generation AI compute. We’re looking for a hands‑on technical leader to pioneer industry-first packaging solutions that integrate power delivery chiplets directly into advanced substrates.
This is not a maintenance role—you will define the architecture, build the process from the ground up, and solve problems no one has solved before. Your work will directly enable breakthroughs in performance, power efficiency, and system scalability for hyperscalers and next‑gen AI platforms.
Why This Role Matters
You will define a new class of packaging architecture that unlocks the next wave of AI compute. This is a rare opportunity to build something truly first of its kind and see it adopted at scale across the industry.
Key Responsibilities – What You’ll Do
Lead the end-to-end development of advanced IC packaging solutions integrating power delivery chiplets into package substrates.
Architect and deliver first‑of‑its‑kind land‑side assembly and embedded chiplet integration within substrate cores.
Build packaging technologies from concept through high‑volume manufacturing (HVM), including design, materials, process, and reliability.
Establish and optimize Design of Experiments (DoE) frameworks to accelerate process development, yield learning, and performance optimization.
Develop statistical models and apply rigorous data analysis to drive design decisions, process control, and yield improvement.
Drive assembly process development, including novel flows for chiplet integration, substrate embedding, and advanced interconnects.
Partner directly with hyperscalers, ASIC, GPU, and xPU customers to integrate power delivery chiplets into their platforms.
Work closely with OSATs, substrate vendors, and materials suppliers to build scalable, manufacturable solutions.
Minimum Qualifications – What You Bring
a Hybrid role requiring 3 days a week onsite in Chandler, AZ.
While we are primarily seeking hyrid candidates for our Chandler, AZ office, remote flexibility may be considered for exceptional candidates in the Greater Phoenix Area or the Greater Portland Area / Vancouver, Washington area (HQ's)
Advanced degree (MS/PhD preferred) in Electrical Engineering, Materials Science, Mechanical Engineering, or related field.
10+ years of experience in semiconductor packaging with deep expertise in advanced packaging (2.5D/3D, chiplets, substrate integration).
Proven experience taking packaging technologies from early concept to production.
Strong background in power delivery, signal/power integrity, and package‑system co‑design.
Hands‑on experience with DoE methodology, statistical analysis, and process optimization in a manufacturing or R&D environment.
Deep expertise in failure analysis, including root cause identification and corrective action across multiple domains.
Strong understanding of soldering processes, interconnect reliability, and assembly defect mechanisms.
Experience working with external manufacturing partners (OSATs) and supply chain ecosystems.
Ability to operate in ambiguity, move fast, and make high‑quality technical decisions with limited data.
Compensation & Benefits
Anticipated annual base salary for Member of Technical Staff: $200,000 - $250,000
Stock option grant
Comprehensive benefits package including health, dental, vision, and 401(k)
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Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.
About the Role
We’re a fast-moving startup building the foundation for next-generation AI compute. We’re looking for a hands‑on technical leader to pioneer industry-first packaging solutions that integrate power delivery chiplets directly into advanced substrates.
This is not a maintenance role—you will define the architecture, build the process from the ground up, and solve problems no one has solved before. Your work will directly enable breakthroughs in performance, power efficiency, and system scalability for hyperscalers and next‑gen AI platforms.
Why This Role Matters
You will define a new class of packaging architecture that unlocks the next wave of AI compute. This is a rare opportunity to build something truly first of its kind and see it adopted at scale across the industry.
Key Responsibilities – What You’ll Do
Lead the end-to-end development of advanced IC packaging solutions integrating power delivery chiplets into package substrates.
Architect and deliver first‑of‑its‑kind land‑side assembly and embedded chiplet integration within substrate cores.
Build packaging technologies from concept through high‑volume manufacturing (HVM), including design, materials, process, and reliability.
Establish and optimize Design of Experiments (DoE) frameworks to accelerate process development, yield learning, and performance optimization.
Develop statistical models and apply rigorous data analysis to drive design decisions, process control, and yield improvement.
Drive assembly process development, including novel flows for chiplet integration, substrate embedding, and advanced interconnects.
Partner directly with hyperscalers, ASIC, GPU, and xPU customers to integrate power delivery chiplets into their platforms.
Work closely with OSATs, substrate vendors, and materials suppliers to build scalable, manufacturable solutions.
Minimum Qualifications – What You Bring
a Hybrid role requiring 3 days a week onsite in Chandler, AZ.
While we are primarily seeking hyrid candidates for our Chandler, AZ office, remote flexibility may be considered for exceptional candidates in the Greater Phoenix Area or the Greater Portland Area / Vancouver, Washington area (HQ's)
Advanced degree (MS/PhD preferred) in Electrical Engineering, Materials Science, Mechanical Engineering, or related field.
10+ years of experience in semiconductor packaging with deep expertise in advanced packaging (2.5D/3D, chiplets, substrate integration).
Proven experience taking packaging technologies from early concept to production.
Strong background in power delivery, signal/power integrity, and package‑system co‑design.
Hands‑on experience with DoE methodology, statistical analysis, and process optimization in a manufacturing or R&D environment.
Deep expertise in failure analysis, including root cause identification and corrective action across multiple domains.
Strong understanding of soldering processes, interconnect reliability, and assembly defect mechanisms.
Experience working with external manufacturing partners (OSATs) and supply chain ecosystems.
Ability to operate in ambiguity, move fast, and make high‑quality technical decisions with limited data.
Compensation & Benefits
Anticipated annual base salary for Member of Technical Staff: $200,000 - $250,000
Stock option grant
Comprehensive benefits package including health, dental, vision, and 401(k)
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