FPGA Engineer
Leidos Inc, San Diego, CA, United States
Leidos Defense Space Business Area is seeking a
FPGA Engineer
to join our team in San Diego, CA.
Primary Responsibilities
Develop and test FPGA designs for Chemical, Biological, Radiation, Nuclear, and Space sensor systems for federal government customers.
Develop and execute FPGA test plans, determine root cause of test failures, and iterate with senior staff to determine design changes to improve FPGA performance.
Support electrical engineering activities including FPGA designs and system integration and testing with CAD and lab activities.
Collaborate with a multi-disciplined design team to design and integrate DSP applications for latest System on a Chip (SoC) implementations such as Xilinx Zynq Ultrascale+ and Xilinx RFSoC.
Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.
Able to synthesize, place and route, meeting timing requirements from high‑speed FPGAs.
Analyze, design, simulate, and implement designs which interface to common signaling standards, typical IP hard macros such as SERDES, PLLs, etc. and/or protocols such PCIe, 10GBE Ethernet, LVDS, etc.
Use judgment to perform technical troubleshooting and diagnosis of failed equipment and support root‑cause analysis.
Perform data analysis and write technical reports.
Develop and maintain design documents, functional requirements and interface control documents.
Basic Qualifications
BS and 5+ years of relevant experience as an electrical engineer or computer engineer in an R&D environment or Masters with 3+ years of relevant experience.
Experience or coursework related to testing FPGA or CPLD designs in an electronics lab.
Fluent in Vivado, Modelsim or Riviera. Fluent in testbenches and self‑checking verification methods.
Working knowledge of electronics test equipment like function generators, oscilloscopes, logic analyzers, and lab power supplies.
Well‑organized, reliable, attention to detail, demonstrated personal initiative. Ability to multi‑task and prioritize workload. Good interpersonal skills and ability to coordinate work with others. Good oral and written communication skills.
Experience working with cross‑functional R&D development teams.
Motivated self‑starter able to work under minimal supervision and an entrepreneurial approach to roles and responsibilities.
US Citizenship is required and must be able to obtain/maintain a Top Secret Security Clearance.
Familiarity with GIT, JIRA, Agile, Scrum.
Preferred Qualifications
Masters' degree or higher in Electrical/Computer Engineering with emphasis on digital/ASIC/FPGA design is a plus.
Breadth of experience in a complementary discipline ability to develop image processing algorithms in Matlab and implement them in HDL, FPGA design, or embedded software is a plus.
Experience with Microchip Polarfire and Libero tools is a plus.
Experience reviewing and documenting technical data packages for military products.
Demonstrated mid‑level lead position in a large FPGA project.
Active Clearance.
Pay and Benefits
Pay Range: $87,100 - $157,450.
Commitment to Non-Discrimination
All qualified applicants will receive consideration for employment without regard to sex, race, ethnicity, age, national origin, citizenship, religion, physical or mental disability, medical condition, genetic information, pregnancy, family structure, marital status, ancestry, domestic partner status, sexual orientation, gender identity or expression, veteran or military status, or any other basis prohibited by law. Leidos will also consider for employment qualified applicants with criminal histories consistent with relevant laws.
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FPGA Engineer
to join our team in San Diego, CA.
Primary Responsibilities
Develop and test FPGA designs for Chemical, Biological, Radiation, Nuclear, and Space sensor systems for federal government customers.
Develop and execute FPGA test plans, determine root cause of test failures, and iterate with senior staff to determine design changes to improve FPGA performance.
Support electrical engineering activities including FPGA designs and system integration and testing with CAD and lab activities.
Collaborate with a multi-disciplined design team to design and integrate DSP applications for latest System on a Chip (SoC) implementations such as Xilinx Zynq Ultrascale+ and Xilinx RFSoC.
Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.
Able to synthesize, place and route, meeting timing requirements from high‑speed FPGAs.
Analyze, design, simulate, and implement designs which interface to common signaling standards, typical IP hard macros such as SERDES, PLLs, etc. and/or protocols such PCIe, 10GBE Ethernet, LVDS, etc.
Use judgment to perform technical troubleshooting and diagnosis of failed equipment and support root‑cause analysis.
Perform data analysis and write technical reports.
Develop and maintain design documents, functional requirements and interface control documents.
Basic Qualifications
BS and 5+ years of relevant experience as an electrical engineer or computer engineer in an R&D environment or Masters with 3+ years of relevant experience.
Experience or coursework related to testing FPGA or CPLD designs in an electronics lab.
Fluent in Vivado, Modelsim or Riviera. Fluent in testbenches and self‑checking verification methods.
Working knowledge of electronics test equipment like function generators, oscilloscopes, logic analyzers, and lab power supplies.
Well‑organized, reliable, attention to detail, demonstrated personal initiative. Ability to multi‑task and prioritize workload. Good interpersonal skills and ability to coordinate work with others. Good oral and written communication skills.
Experience working with cross‑functional R&D development teams.
Motivated self‑starter able to work under minimal supervision and an entrepreneurial approach to roles and responsibilities.
US Citizenship is required and must be able to obtain/maintain a Top Secret Security Clearance.
Familiarity with GIT, JIRA, Agile, Scrum.
Preferred Qualifications
Masters' degree or higher in Electrical/Computer Engineering with emphasis on digital/ASIC/FPGA design is a plus.
Breadth of experience in a complementary discipline ability to develop image processing algorithms in Matlab and implement them in HDL, FPGA design, or embedded software is a plus.
Experience with Microchip Polarfire and Libero tools is a plus.
Experience reviewing and documenting technical data packages for military products.
Demonstrated mid‑level lead position in a large FPGA project.
Active Clearance.
Pay and Benefits
Pay Range: $87,100 - $157,450.
Commitment to Non-Discrimination
All qualified applicants will receive consideration for employment without regard to sex, race, ethnicity, age, national origin, citizenship, religion, physical or mental disability, medical condition, genetic information, pregnancy, family structure, marital status, ancestry, domestic partner status, sexual orientation, gender identity or expression, veteran or military status, or any other basis prohibited by law. Leidos will also consider for employment qualified applicants with criminal histories consistent with relevant laws.
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