Senior Bring up Methodology Lead
NVIDIA AI, Santa Clara, CA, United States
NVIDIA Silicon Codesign Group is seeking a versatile engineer to be part of the HW bring‑up methodology team. The SCG team is uniquely positioned to have an end‑to‑end view of the product development cycle – from early architecture definition, through bring‑up, to product release.
What Will You Be Doing
Lead end‑to‑end planning and on‑time execution of Nvidia’s new chip bring‑up effort, from pre‑silicon through production deployment.
Coordinate multi‑functional teams across Architecture, Design, Validation, DFT, SW, System, and Operations to drive shared bring‑up milestones.
Improve cross‑team communication, coordination, and handoffs between teams.
Develop and standardize methodologies, processes, and workflows for silicon bring‑up, creating reusable checklists and playbooks.
Drive scheduling, equipment, and material logistics to support ambitious NPI and production schedules.
Lead post‑action reviews and convert key findings into concrete process improvements for future silicon and solution bring‑ups.
Contribute to post‑silicon learnings that feed back into architecture, design, and pre‑silicon validation to improve the next generation.
Serve as the central point of contact for bring‑up timeline status, risks, and mitigations for leadership.
What We Need To See
MS in Engineering or related field, or equivalent experience.
10+ years of experience leading complex, multi‑site technical programs in semiconductor, SoC, or system/platform development.
Proven experience influencing decisions and leading multi‑functional teams in a fast‑paced, highly technical environment.
Background in silicon or system bring‑up.
Strong leadership and problem‑solving skills with the ability to think strategically about end‑to‑end silicon solution readiness and tactically about day‑to‑day execution.
Enthusiastic, responsive, and passionate about process improvement, with a track record of identifying gaps and driving better methodologies.
Excellent communication and interpersonal skills; able to align diverse interested parties and drive clear, timely decisions.
Ways To Stand Out From The Crowd
Hands‑on experience with first‑silicon bring‑up, post‑silicon validation, or silicon debug for complex chips and or systems.
Experience driving transitions from NPI to HVM, including readiness criteria, sign‑off processes, and ramp optimization.
Familiarity with lab operations, validation infrastructure, and common tools used in hardware bring‑up.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $196,000 USD – $310,500 USD for Level 5, and $232,000 USD – $368,000 USD for Level 6. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until April 13, 2026.
NVIDIA is committed to fostering a diverse work environment and is an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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What Will You Be Doing
Lead end‑to‑end planning and on‑time execution of Nvidia’s new chip bring‑up effort, from pre‑silicon through production deployment.
Coordinate multi‑functional teams across Architecture, Design, Validation, DFT, SW, System, and Operations to drive shared bring‑up milestones.
Improve cross‑team communication, coordination, and handoffs between teams.
Develop and standardize methodologies, processes, and workflows for silicon bring‑up, creating reusable checklists and playbooks.
Drive scheduling, equipment, and material logistics to support ambitious NPI and production schedules.
Lead post‑action reviews and convert key findings into concrete process improvements for future silicon and solution bring‑ups.
Contribute to post‑silicon learnings that feed back into architecture, design, and pre‑silicon validation to improve the next generation.
Serve as the central point of contact for bring‑up timeline status, risks, and mitigations for leadership.
What We Need To See
MS in Engineering or related field, or equivalent experience.
10+ years of experience leading complex, multi‑site technical programs in semiconductor, SoC, or system/platform development.
Proven experience influencing decisions and leading multi‑functional teams in a fast‑paced, highly technical environment.
Background in silicon or system bring‑up.
Strong leadership and problem‑solving skills with the ability to think strategically about end‑to‑end silicon solution readiness and tactically about day‑to‑day execution.
Enthusiastic, responsive, and passionate about process improvement, with a track record of identifying gaps and driving better methodologies.
Excellent communication and interpersonal skills; able to align diverse interested parties and drive clear, timely decisions.
Ways To Stand Out From The Crowd
Hands‑on experience with first‑silicon bring‑up, post‑silicon validation, or silicon debug for complex chips and or systems.
Experience driving transitions from NPI to HVM, including readiness criteria, sign‑off processes, and ramp optimization.
Familiarity with lab operations, validation infrastructure, and common tools used in hardware bring‑up.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $196,000 USD – $310,500 USD for Level 5, and $232,000 USD – $368,000 USD for Level 6. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until April 13, 2026.
NVIDIA is committed to fostering a diverse work environment and is an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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