Signal Engineer

Lead Signal Integrity Engineer - San Fransisco - $160,000 - $245,000 + Benefits

The Role In this highly visible leadership position, you will join our SI/PI team to drive the modelling, analysis, and simulation of Signal and Power Integrity within the challenging DDR landscape, specifically focusing on speeds of 12800+ MT/s. Reporting directly to the VP of Engineering, you will define methodologies for our latest product portfolio and work cross-functionally with design, validation, and customers to ensure superior performance.
Key Responsibilities

Methodology & Design:

Create SI/PI methodologies and perform package design studies for the latest DDR products.
System Architecture:

Define specifications for packaging, PCB routing, IC-PKG-BRD decoupling, and jitter sensitivity.
Technical Leadership:

Provide guidelines to design teams based on simulation and silicon correlation to achieve best-in-class RMT scores.
Lab & Debug:

Support teams during lab bring-up and debug using high-end characterization tools.
Collaboration:

Work directly with customers to find optimum SI/PI solutions for complex system-level integrations.
Requirements

Education:

MS or PhD in Electrical Engineering.
Experience:

10+ years of industry experience, including significant exposure to

DDR4/5

or

SERDES

interfaces.
Theory:

Solid mastery of EM, transmission line theory, and equalization techniques (FIR, FFE, DFE, CTLE).
Tools:

Proficiency in ADS, Spice, HFSS, Q3D, or PowerSI. Ability to edit APD/Allegro layout files is required.
Lab Skills:

Experience correlating simulation results with lab measurements (Scopes, TDRs, VNAs).
Systems Knowledge:

Deep understanding of server systems, from CPUs to DRAMs on DIMM modules.

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