Senior Director Digital Design - 16907

What You’ll Be Doing

Lead digital design for high-speed die-to-die interconnect ICs from microarchitecture through physical design handoff

Direct RTL development, logic synthesis, timing closure, and clock domain crossing verification

Oversee DFT implementation including scan insertion, ATPG, MBIST, and boundary scan

Manage verification strategy, testbench architecture, assertion-based verification, and coverage closure

Guide pre-silicon validation using emulation platforms for link training and error recovery testing

Conduct technical reviews of microarchitecture, RTL quality, synthesis QoR, and verification plans

The Impact You Will Have

You will establish RTL architecture and implementation methodology for interconnect IPs enabling next-generation AI systems

Your synthesis and timing strategies will determine whether designs meet frequency targets within power budgets

The verification infrastructure you develop will impact first-silicon success and reduce debug cycles

Your DFT architecture will influence test coverage, yield learning, and production test economics

Your technical decisions on clock architecture and datapath optimization will affect product competitiveness

What You’ll Need

15+ years digital design experience with multiple high-speed ASIC tapeouts, including 5+ years in technical leadership

Strong expertise in SystemVerilog RTL design including complex FSMs, pipelined datapaths, and clock domain crossing

Demonstrated experience with logic synthesis and timing closure on multi-GHz designs

Proven background in high-speed digital design for SerDes, PHY, or die-to-die interconnect

Comprehensive DFT experience including scan design, ATPG, MBIST, and boundary scan

Solid foundation in digital verification including UVM, assertions, and formal verification

Who You Are

You analyze timing reports and distinguish architectural issues from transient concerns

You evaluate verification plans for completeness, identifying gaps in corner case coverage

You assess RTL for synthesis implications, recognizing structures that create timing or area challenges

You make informed tradeoffs between latency, throughput, power, and area based on requirements

You have developed engineers in metastability handling, gray code crossing, and low-latency optimization

The Team You’ll Be Part Of
You will lead the digital design organization within Silicon Engineering, focused on high-bandwidth, ultra-low-latency die-to-die links for AI compute and networking systems. The team covers RTL design, logic synthesis, timing closure, DFT, digital verification, emulation, and program execution. You will work with analog design on PHY interfaces, physical implementation on timing closure, and system architects on protocol and performance requirements.

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