Director - ASIC Design Verification - Terawave

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed.Position Summary We are seeking an experienced ASIC Design Verification Director to lead the verification of advanced digital ASICs and SoCs for satellite communications applications, driving verification strategy, methodology, and quality across programs and product generations.Core Responsibilities Lead verification of complex digital ASIC and SoC designs for satellite communications applications.Define and implement verification strategy across block, subsystem, and SoC levels.Drive development of robust verification environments using System Verilog, UVM, assertions, coverage‑driven verification, and formal methods.Ensure comprehensive verification of datapath, control, interface, protocol, and integration behavior.Establish verification signoff criteria and drive closure for functional coverage, regressions, assertions, and quality metrics.Partner closely with ASIC design, systems engineering, architecture, DFT, physical design, FPGA, firmware, validation, and program management teams.Build, lead, and develop high‑performing verification teams through hiring, mentoring, and performance management.Set priorities, allocate resources, and align staffing with program schedules and technical needs.Improve verification methodology, reusable infrastructure, automation frameworks, and development processes.Support emulation, FPGA prototyping, silicon bring‑up, and pre‑silicon/post‑silicon correlation activities as needed.Minimum Qualifications BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.Strong experience in ASIC/SoC verification for complex digital designs.Deep expertise in System Verilog and UVM.Strong understanding of constrained‑random verification, functional coverage, assertions, scoreboards, reference models, regression planning, debug, and verification closure.Experience verifying high‑performance digital systems with both control logic and high‑throughput datapaths.Proven technical leadership and multi‑functional execution skills.Strong communication, organizational, and problem‑solving skills.For Manager level: typically 8+ years of ASIC/SoC verification experience, including leadership of a verification team, major subsystem, or chip partition.For Director level: typically 12+ years of ASIC/SoC verification experience and 5+ years of people management experience, including leadership of senior engineers, leads, and/or managers.Preferred Qualifications Experience with modem, baseband, DSP, beamforming, or networking ASICs.Familiarity with aerospace or high‑reliability system development.Experience supporting silicon bring‑up and post‑silicon debug.Compensation Compensation Range for CA applicants: $233,934.00 - $327,506.55. For WA applicants: $233,934.00 - $327,506.55. Other site ranges may differ.Benefits Medical, dental, vision, basic and supplemental life insurance.Paid parental leave.Short‑ and long‑term disability.401(k) with a company match of up to 5% and an Education Support Program.Stock options.Paid time off: up to four (4) weeks per year plus up to 14 company‑paid holidays.Optional bonuses and incentives (subject to company discretion).Equal Employment Opportunity Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated workforce. We support the establishment and maintenance of a workplace that fosters trust, equality, and teamwork. We provide all qualified applicants for employment and employees with equal opportunities for hire, promotion, and other terms and conditions of employment, regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, age, physical or mental disability, genetic factors, military/veteran status, or any other status or characteristic protected by federal, state, and/or local law. Blue Origin will consider for employment qualified applicants with criminal histories in a manner consistent with applicable federal, state, and local laws, including the Washington Fair Chance Act, the California Fair Chance Act, and the Los Angeles Fair Chance in Hiring Ordinance, and other applicable laws.#J-18808-Ljbffr