Intel is seeking a Mixed Signal Logic Design Engineer in Santa Clara, California. This role involves developing specifications, running simulations, and ensuring design integrity for high-speed and mixed signal IP designs. Ideal candidates possess experience with SystemVerilog and digital design concepts.
Competitive compensation includes a salary that ranges from $141,910 to $269,100, based on various factors including location and experience. Join us to drive innovation and impact within a collaborative environment.
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Impactful Mixed-Signal Logic Design Engineer
Intel · Multiple locations ·
- Pay:
- $141,910-$269,100/yr
- Job type:
- Full Time