Video Codec Verification Engineer (ASIC/FPGA)

ByteDance is seeking a Design Verification Engineer to help deliver a Video Codec IP by generating test benches and running simulations. You will interface with architects and ASIC/FPGA design engineers to develop test plans, lead bug tracking, and automation of regression testing.
The role requires hands-on experience with SystemVerilog, UVM, SystemC, DPI, and scripting (Perl, Python, Tcl, Unix-shell). Proficiency with VCS and Verdi for waveform debugging is essential.

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