ByteDance in San Jose is seeking an ASIC Design Engineer Graduate (Video Silicon IP) for a 2027 start. You will join the Technology team to design hardware accelerators for video encoding and processing on FPGA/ASIC, working with experts across algorithm, architecture, software, firmware and verification.
As a graduate, you will explore bold ideas, tackle challenging problems, and grow quickly. Applicants should be finishing a Master's in CS or EE, with knowledge of video codecs and RTL
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