High-Performance Video Codec ASIC Engineer

ByteDance seeks a video codec hardware design engineer to develop RTL for high-performance video encoding IP (FPGA/ASIC). You will collaborate with architecture, algorithms, and verification teams to deliver scalable, power-efficient codecs and multi-standard blocks, translating standards into implementable hardware.
Strong SystemVerilog, UVM, and Python skills are required. Ideal candidates hold a MS/PhD in EE or CE, 2+ years in front-end ASIC design, and experience with SV/HLS, AXI interfaces,

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