Senior Analog IC Layout Engineer – High-Performance CMOS (3/5nm)

A tech solutions company is seeking an experienced Analog Layout Engineer in Santa Clara, CA. The ideal candidate will have over 10 years of experience in high-performance analog layout within advanced CMOS processes, leading IC layouts, and working with EDA tools like Cadence and Mentor. Responsibilities include debugging verification issues and adhering to project schedules. Join a dynamic team focused on cutting-edge technology with opportunities for career growth. #J-18808-Ljbffr