We are seeking a Senior Analog Layout Engineer responsible for the layout of high-performance analog cores, including Client, DAC, PLLs, and transceivers. This role involves leading IC layout for cutting-edge, high-speed CMOS integrated circuits using advanced foundry process nodes.
Key Responsibilities:Lead IC layout for high-performance, high-speed CMOS integrated circuits.
Perform analog layout for blocks such as ADCs, DACs, PLLs, references, and transceivers.
Work with advanced foundry CMOS process nodes (3nm, 5nm, 7nm, 16nm).
Execute floorplanning, block-level routing, and top-level chip assembly.
Apply industry best practices for high-performance analog layout.
Set up and debug LVS, DRC, and ERC verification environments.
Collaborate with distributed design teams to meet project schedules.
Required Qualifications:10+ years of experience in high-performance analog layout using advanced CMOS process nodes.
Strong expertise with industry-standard EDA tools from Cadence, Mentor, and Synopsys.
Proven experience setting up and debugging LVS, DRC, and ERC.
In-depth knowledge of analog layout techniques, including:
Shielding and dummy devices
Thermal-aware layout and electromigration considerations
Demonstrated experience delivering analog layout for silicon chips in mass production
Strong written and verbal communication skills
Self-starter with the ability to define and adhere to project schedules
Preferred Skills:Experience with FinFET process nodes.
Knowledge of SKILL scripting and layout automation.
Experience working with globally distributed design teams.
Mandatory Skills:LVS, DRC, ERC verification
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Key Responsibilities:Lead IC layout for high-performance, high-speed CMOS integrated circuits.
Perform analog layout for blocks such as ADCs, DACs, PLLs, references, and transceivers.
Work with advanced foundry CMOS process nodes (3nm, 5nm, 7nm, 16nm).
Execute floorplanning, block-level routing, and top-level chip assembly.
Apply industry best practices for high-performance analog layout.
Set up and debug LVS, DRC, and ERC verification environments.
Collaborate with distributed design teams to meet project schedules.
Required Qualifications:10+ years of experience in high-performance analog layout using advanced CMOS process nodes.
Strong expertise with industry-standard EDA tools from Cadence, Mentor, and Synopsys.
Proven experience setting up and debugging LVS, DRC, and ERC.
In-depth knowledge of analog layout techniques, including:
Shielding and dummy devices
Thermal-aware layout and electromigration considerations
Demonstrated experience delivering analog layout for silicon chips in mass production
Strong written and verbal communication skills
Self-starter with the ability to define and adhere to project schedules
Preferred Skills:Experience with FinFET process nodes.
Knowledge of SKILL scripting and layout automation.
Experience working with globally distributed design teams.
Mandatory Skills:LVS, DRC, ERC verification
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