Senior Analog Layout Engineer - High-Speed CMOS ICs

A leading technology firm is seeking a Senior Analog Layout Engineer to lead high-performance analog layout for cutting-edge CMOS integrated circuits. The ideal candidate has over 10 years of experience and expertise with tools from Cadence, Mentor, and Synopsys. Responsibilities include executing analog layout for various blocks, collaborating with distributed teams, and applying industry best practices. Strong communication skills and self-motivation are essential. This role is vital for ensuring successful project outcomes in a fast-paced environment. #J-18808-Ljbffr