IC Layout Engineer - High-Density CMOS & Tapeout

A technology company in Santa Barbara, CA, seeks an IC layout engineer to perform CMOS mixed-signal layout for readout integrated circuits. Responsibilities include chip floor planning, collaborating on designs, and enhancing EDA tool efficiency. The ideal candidate will have a Bachelor's degree in electrical engineering, two years of experience, and strong teamwork skills. The position offers a salary range of $100,000 to $140,000 annually and benefits including paid time off and insurance. #J-18808-Ljbffr