Sr Principal ASIC Design Engineer: Lead High-Perf Silicon

A global technology company in Santa Clara is seeking a skilled ASIC designer to lead module design for next-generation firewall platforms. This role requires over 10 years of experience in front-end ASIC design and expertise in SystemVerilog RTL. Responsibilities include developing specifications, designing and verifying RTL, and collaborating with engineering teams. The position offers a competitive salary range between $173,600.00 and $280,700.00 annually, reflecting qualifications and experience.
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