Senior ASIC RTL Design Engineer for High-Perf Networking

A high-tech company in Santa Clara is seeking an experienced ASIC Design Engineer. You will define and document micro-architecture and collaborate with cross-functional teams to ensure design integrity. The ideal candidate will have over 8 years of relevant technical experience and a proven record in logic design for complex ASICs. This role offers a competitive salary range of $100,000 to $500,000 based on experience, in a culture that values diversity and inclusion.
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