Junior RTL Design Engineer — Grow with AI ASICs

A high-tech company in Santa Clara is seeking an experienced engineer to join their ASIC Design team. The role involves designing micro-architectures, collaborating with cross-functional teams, and ensuring logic design meets specific performance targets. The ideal candidate has at least 2 years of ASIC design experience and a degree in electrical or computer engineering. The compensation range for technical roles is competitive, and a commitment to diversity and inclusion is emphasized.
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