ASIC Chip Design Lead
InterSources Inc, Saratoga, CA, United States
Strong hands-on experience with RTL design and micro-architecture
Proven experience with full-chip integration and timing closure
Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
Deep understanding of synthesis, static timing analysis, and physical-design collaboration
Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
Demonstrated ability to drive execution in ambiguous, fast-moving environments
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Proven experience with full-chip integration and timing closure
Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
Deep understanding of synthesis, static timing analysis, and physical-design collaboration
Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
Demonstrated ability to drive execution in ambiguous, fast-moving environments
#J-18808-Ljbffr