Senior ASIC Design Lead: RTL, Tape-Out & Architecture

A Silicon Valley hardware startup is seeking a hands-on ASIC Chip Design Lead to manage chip design execution from micro-architecture through integration and timing signoff. This role requires expertise in RTL design and the ability to lead across design teams in a fast-paced environment. The position offers a competitive salary range of $250,000 to $280,000 per year in Saratoga, CA, and an opportunity to work on groundbreaking AI infrastructure technology.
#J-18808-Ljbffr