Mediabistro logo
job logo

Senior ASIC RTL Design Engineer — Tape-out Expert

AMD, San Jose, CA, United States


A leading semiconductor company in California is seeking a Senior ASIC Design Engineer to join their Silicon Design team. In this role, you will be responsible for driving the complete RTL design lifecycle for embedded products. The ideal candidate will have proven expertise in Verilog RTL coding, timing closure, and the complete ASIC design flow. The position offers competitive benefits and a collaborative work environment focused on innovation and excellence.
#J-18808-Ljbffr