Senior ASIC Design Engineer – High-Performance Silicon

A leading aerospace manufacturer located in Irvine, CA is seeking a Senior ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink project. This role requires a Bachelor's degree in electrical engineering and 5+ years of experience in RTL implementation. You will work with cross-disciplinary teams, tackling complex problems, defining micro-architecture, and ensuring silicon timing closure. Competitive pay between $160,000 and $220,000 per year, with comprehensive benefits including medical coverage and stock options.
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