RTL Design Engineer
Teradyne, North Reading, MA, United States
Opportunity Overview
Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne’s next-generation products such as SOC and Memory Test Instruments. You will join a best-in-class Digital team as an RTL Designer, collaborating with an Analog team and product architects to develop next-generation large mixed-signal ASICs. Your responsibilities include specification, architecture, design, verification, physical design, silicon bringup, and the use of AI tools to optimize productivity.
Responsibilities
Develop specifications, micro-architecture, and RTL design of mission-critical blocks in collaboration with the chip architect.
Integrate industry-standard and Teradyne custom IPs.
Collaborate with the verification team on test plans, debug support, and coverage closure to ensure high-quality RTL and first-pass silicon success.
Provide timing constraints and STA support to the Physical Design team for timing closure.
Assist with post-silicon lab bringup and debug support.
Qualifications
BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
Extensive logic design experience writing RTL in Verilog.
Design of state machines, FIFOs, high-speed data paths, arbitration logic, and DFT.
Experience with logic synthesis and timing constraints.
Experience with clock domain crossings (CDC) and static timing analysis (STA).
Experience with high-speed memory and serial interfaces.
Experience with automation through scripting such as Python, Tcl, and Make.
Compensation
The base salary range for this role is $123,100 - $196,900. This range is a good faith estimate and may fluctuate depending on demand and location.
Incentive Plan
This job is eligible for discretionary bonus(es) based on financial performance.
Benefits
Teradyne offers comprehensive health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.
Equal Opportunity Statement
We are an equal‑opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will provide reasonable accommodation for individuals with disabilities to participate in the application, interview process, and to perform essential job functions.
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Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne’s next-generation products such as SOC and Memory Test Instruments. You will join a best-in-class Digital team as an RTL Designer, collaborating with an Analog team and product architects to develop next-generation large mixed-signal ASICs. Your responsibilities include specification, architecture, design, verification, physical design, silicon bringup, and the use of AI tools to optimize productivity.
Responsibilities
Develop specifications, micro-architecture, and RTL design of mission-critical blocks in collaboration with the chip architect.
Integrate industry-standard and Teradyne custom IPs.
Collaborate with the verification team on test plans, debug support, and coverage closure to ensure high-quality RTL and first-pass silicon success.
Provide timing constraints and STA support to the Physical Design team for timing closure.
Assist with post-silicon lab bringup and debug support.
Qualifications
BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
Extensive logic design experience writing RTL in Verilog.
Design of state machines, FIFOs, high-speed data paths, arbitration logic, and DFT.
Experience with logic synthesis and timing constraints.
Experience with clock domain crossings (CDC) and static timing analysis (STA).
Experience with high-speed memory and serial interfaces.
Experience with automation through scripting such as Python, Tcl, and Make.
Compensation
The base salary range for this role is $123,100 - $196,900. This range is a good faith estimate and may fluctuate depending on demand and location.
Incentive Plan
This job is eligible for discretionary bonus(es) based on financial performance.
Benefits
Teradyne offers comprehensive health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.
Equal Opportunity Statement
We are an equal‑opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will provide reasonable accommodation for individuals with disabilities to participate in the application, interview process, and to perform essential job functions.
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