RTL Design Engineer – High-Speed ASICs & Bringup

Teradyne is hiring an RTL Designer in North Reading, Massachusetts, responsible for developing advanced ASICs for next-generation test instruments. The role involves collaborating with analog teams and chip architects, with a focus on RTL design, integration of IPs, and ensuring high-quality deliverables through verification. Candidates should have a BSEE or MSEE and 5+ years of experience in logic design and automation scripting. Comprehensive benefits and a competitive salary range from $123,100 - $196,900 are offered.
#J-18808-Ljbffr