Senior RTL/ASIC Design Engineer — Full-Cycle IP & SoC

A leading semiconductor company located in San Jose, CA, is seeking a Senior ASIC Design Engineer. This role involves owning the complete RTL design lifecycle for cutting-edge IPs targeted at next-generation embedded products. The ideal candidate will have proven expertise in Verilog RTL coding, experience in multiple production tape-outs, and the ability to mentor junior engineers. Join us to shape the future of AI and advanced computing systems, with a focus on innovation and teamwork.
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