Senior RTL/SoC Design Engineer for AI ASICs

A leading technology company in San Jose is seeking an experienced ASIC/SoC Engineer to lead RTL design, simulation, and verification efforts. The ideal candidate will have a strong background in electrical engineering with expertise in RTL design, Verilog, and System Verilog. This role offers an opportunity to mentor junior engineers while contributing to innovative technology for AI computations. The salary range is competitive, offering between $110,000 - $300,000 annually based on experience.
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