RTL/SoC Design Engineer — ASIC & IP Integration Leader

A leading technology company is seeking an ASIC RTL/SoC Design Engineer in San Jose, CA, to lead RTL design and verification of cutting-edge products. The ideal candidate will possess a master's or PhD in Electrical Engineering, have extensive experience using Verilog and System Verilog, and work collaboratively across teams. A strong understanding of complex SoC and digital design is essential, along with leadership skills in a startup environment. This role offers a competitive salary range of $110,000 - $300,000 per year.
#J-18808-Ljbffr