ASIC RTL Design Engineer — SoC Performance & IP

A leading technology company in Austin is seeking an ASIC Design Engineer to join their team. The role focuses on defining and delivering methodologies for system-level IP, requiring a strong academic background in digital design and computer architecture. Candidates should have programming experience in Python, knowledge of Verilog RTL design, and excellent problem-solving skills. The position offers a competitive salary and a commitment to diversity in the workplace.
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