ASIC Methodology Developer
ManpowerGroup, San Jose, CA, United States
Our client, a leading organization in the semiconductor industry, is seeking a ASIC CAD/EDA Flow/Methodology Developer to join their team. As a ASIC CAD/EDA Flow/Methodology Developer, you will be part of the Engineering Department supporting the design and development teams. The ideal candidate will have strong analytical skills, excellent communication, and a proactive mindset, which will align successfully in the organization.
Job Title
ASIC CAD/EDA Flow/Methodology Developer
Location
San Jose, California
What's the Job?
Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data-driven approach.
Knowledge of signoff closure - Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level.
Experience in Block-level and Full-chip integration.
Understanding constraints and fixing design/timing techniques.
Interpreting LVS, DRC, and ERC reports to find the fastest way to complete layout.
What's Needed?
8+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advanced nodes including FinFET technologies.
Great understanding of CAD flows and tools related to ASIC/SOC methodologies.
Excellent programming skills in languages: SKILL, Perl; Python is a plus.
Strong fundamentals in software development.
Knowledge with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver.
Benefits
Medical and Prescription Drug Plans
Dental Plan
Vision Plan
Health Savings Account
Health Flexible Spending Account
Dependent Care Flexible Spending Account
Supplemental Life Insurance
Short Term and Long Term Disability Insurance
Business Travel Insurance
401(k), Plus Match
Weekly Pay
EEO Statement
ManpowerGroup is committed to providing equal employment opportunities in a professional, high quality work environment. It is the policy of ManpowerGroup and all of its subsidiaries to recruit, train, promote, transfer, pay and take all employment actions without regard to an employee's race, color, national origin, ancestry, sex, sexual orientation, gender identity, genetic information, religion, age, disability, protected veteran status, or any other basis protected by applicable law.
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Job Title
ASIC CAD/EDA Flow/Methodology Developer
Location
San Jose, California
What's the Job?
Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data-driven approach.
Knowledge of signoff closure - Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level.
Experience in Block-level and Full-chip integration.
Understanding constraints and fixing design/timing techniques.
Interpreting LVS, DRC, and ERC reports to find the fastest way to complete layout.
What's Needed?
8+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advanced nodes including FinFET technologies.
Great understanding of CAD flows and tools related to ASIC/SOC methodologies.
Excellent programming skills in languages: SKILL, Perl; Python is a plus.
Strong fundamentals in software development.
Knowledge with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver.
Benefits
Medical and Prescription Drug Plans
Dental Plan
Vision Plan
Health Savings Account
Health Flexible Spending Account
Dependent Care Flexible Spending Account
Supplemental Life Insurance
Short Term and Long Term Disability Insurance
Business Travel Insurance
401(k), Plus Match
Weekly Pay
EEO Statement
ManpowerGroup is committed to providing equal employment opportunities in a professional, high quality work environment. It is the policy of ManpowerGroup and all of its subsidiaries to recruit, train, promote, transfer, pay and take all employment actions without regard to an employee's race, color, national origin, ancestry, sex, sexual orientation, gender identity, genetic information, religion, age, disability, protected veteran status, or any other basis protected by applicable law.
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