Mixed Signal-ASIC CAD Methodology Developer
Capgemini, San Jose, CA, United States
Mixed Signal-ASIC CAD Methodology Developer
Choosing Capgemini means choosing a company where you will be empowered to shape your career in the way you’d like, where you’ll be supported and inspired bya collaborative community of colleagues around the world, and where you’ll be able to reimagine what’s possible. Join us and help the world’s leading organizations unlock the value of technology and build a more sustainable, more inclusive world.
Location: San Jose, Ca
About the job you’re considering
In this role, you will help shape and evolve Mixed Signal-ASIC CAD and EDA methodologies used to deliver complex designs on advanced process technologies. You will collaborate with design, layout, and physical implementation teams to improve tools, flows, and signoff practices that directly impact silicon quality, performance, and time‑to‑market.
Your Role & Responsibilities
In this role, you will:
Influence and evolve
ASIC / SoC CAD tools, flows, and design methodologies
across design construction, optimization, and sign‑off
Support
block‑level and full‑chip integration , enabling high‑quality, production‑ready layouts
Drive
sign‑off closure , including timing (SI and OCV), power, IR, and physical verification at block and chip level
Interpret and resolve
DRC, LVS, ERC, and PEX
results efficiently to meet program schedules
Apply strong knowledge of
constraints, timing fixes, and SI prevention techniques
Partner with design and layout teams to meet
performance, area, power, and reliability
targets
Leverage
design automation, scripting, and UNIX environments
to improve flow robustness and productivity
Your Skills & Experience
8+ years of experience in analog and mixed‑signal layout design using deep submicron CMOS technologies, including 3+ years of recent experience on advanced nodes such as FinFET.
Strong understanding of Mixed Signal- ASIC/SOC CAD flows and signoff methodologies, including timing, power, IR, and physical verification. Proficient in SKILL and Perl, with a solid foundation in software development.
Python experience is a plus.
Hands‑on experience with EM/IR analysis, DRC/LVS/PEX/ERC, and working through signoff and waiver processes.
Familiar with circuit design fundamentals, including device characteristics, SPICE and Verilog netlists, and simulation concepts.
Experience using industry‑standard EDA tools such as Synopsys ICC/ICC2 and Cadence Innovus/Virtuoso in UNIX/Linux environments.
Demonstration of strong communication and collaboration skills, enabling you to work effectively across engineering disciplines and influence technical outcomes.
The base compensation range for this role in the posted location is: $88,800 up to $187,740 per year.
Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.
The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.
These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.
It is not typical for candidates to be hired at or near the top of the posted compensation range.
In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.
Capgemini offers a comprehensive, non‑negotiable benefits package to all regular, full‑time employees.
In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include:
Paid time off based on employee grade (A‑F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
Life and disability insurance
Employee assistance programs
Other benefits as provided by local policy and eligibility
Important Notice
Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.
Disclaimers
Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.
Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
#J-18808-Ljbffr
Choosing Capgemini means choosing a company where you will be empowered to shape your career in the way you’d like, where you’ll be supported and inspired bya collaborative community of colleagues around the world, and where you’ll be able to reimagine what’s possible. Join us and help the world’s leading organizations unlock the value of technology and build a more sustainable, more inclusive world.
Location: San Jose, Ca
About the job you’re considering
In this role, you will help shape and evolve Mixed Signal-ASIC CAD and EDA methodologies used to deliver complex designs on advanced process technologies. You will collaborate with design, layout, and physical implementation teams to improve tools, flows, and signoff practices that directly impact silicon quality, performance, and time‑to‑market.
Your Role & Responsibilities
In this role, you will:
Influence and evolve
ASIC / SoC CAD tools, flows, and design methodologies
across design construction, optimization, and sign‑off
Support
block‑level and full‑chip integration , enabling high‑quality, production‑ready layouts
Drive
sign‑off closure , including timing (SI and OCV), power, IR, and physical verification at block and chip level
Interpret and resolve
DRC, LVS, ERC, and PEX
results efficiently to meet program schedules
Apply strong knowledge of
constraints, timing fixes, and SI prevention techniques
Partner with design and layout teams to meet
performance, area, power, and reliability
targets
Leverage
design automation, scripting, and UNIX environments
to improve flow robustness and productivity
Your Skills & Experience
8+ years of experience in analog and mixed‑signal layout design using deep submicron CMOS technologies, including 3+ years of recent experience on advanced nodes such as FinFET.
Strong understanding of Mixed Signal- ASIC/SOC CAD flows and signoff methodologies, including timing, power, IR, and physical verification. Proficient in SKILL and Perl, with a solid foundation in software development.
Python experience is a plus.
Hands‑on experience with EM/IR analysis, DRC/LVS/PEX/ERC, and working through signoff and waiver processes.
Familiar with circuit design fundamentals, including device characteristics, SPICE and Verilog netlists, and simulation concepts.
Experience using industry‑standard EDA tools such as Synopsys ICC/ICC2 and Cadence Innovus/Virtuoso in UNIX/Linux environments.
Demonstration of strong communication and collaboration skills, enabling you to work effectively across engineering disciplines and influence technical outcomes.
The base compensation range for this role in the posted location is: $88,800 up to $187,740 per year.
Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.
The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.
These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.
It is not typical for candidates to be hired at or near the top of the posted compensation range.
In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.
Capgemini offers a comprehensive, non‑negotiable benefits package to all regular, full‑time employees.
In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include:
Paid time off based on employee grade (A‑F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
Life and disability insurance
Employee assistance programs
Other benefits as provided by local policy and eligibility
Important Notice
Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.
Disclaimers
Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.
Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
#J-18808-Ljbffr