Senior ASIC Physical Design Engineer — P&R & Signoff

A leading semiconductor company in San Jose is looking for a Physical Design Engineer to oversee the complete APR flow from RTL to GDS. The role includes executing chip implementations, ensuring quality floorplans, and addressing timing closures. Candidates should have a Master's in Electrical/Computer Science Engineering with at least 3 years of experience and proficiency in EDA tools and Perl/TCL programming. The position features a hybrid work model and a competitive salary range of $110,000 to $160,000 annually.
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