Senior ASIC Design Engineer – Co-Packaged Optics

A cutting-edge technology company in San Jose is seeking an ASIC Sr. Staff Engineer responsible for the design and debug of complex digital subsystems. The ideal candidate will have a BS or MS in Electrical Engineering and over 5 years of experience in ASIC design and verification. Proficiency in Verilog, SystemVerilog, and Python is essential. This role offers an opportunity to work in a fast-paced startup environment with competitive remuneration ranging from $180,000 to $223,000.
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