Senior Design Engineer: High-Speed PCIe & Ethernet RTL

A leading technology company is looking for a Design Engineer in Austin, TX. The role involves architecture and RTL implementation of high-speed datapaths, focusing on PCIe and Ethernet protocol integration. Applicants should have expert-level skills in SystemVerilog/Verilog and related industry experience. This position offers a competitive salary ranging from $108,000 to $192,000, along with bonuses and a comprehensive benefits package including health plans, 401(K) matching, and paid leave.
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