Memory Chip Design Engineer
WD, San Jose, CA, United States
WD is seeking a full‑time Research Staff Member in the Design Group of Western Digital’s research department. The role is part of a multi‑functional team focused on developing and commercializing a strategic radiation‑hardened memory technology.
Responsibilities
Develop high‑density memory chip custom layout, including shared operational circuitry and pitch‑line drivers; cover all design phases from architecture definition to tape‑out.
Run and debug physical‑verification flows (DRC, LVS, ERC, antenna checks); minimize parasitic R and C, address reliability issues (electromigration, IR‑drop, DFM robustness).
Coordinate split‑fab design and development between WD memory‑array layers and a CMOS foundry; harmonize wafer requirements, develop EDA tool design rules, and execute split‑fab tape‑out flow.
Qualifications
Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Physics, or a closely related field.
Proven experience in high‑density memory chip layout, tape‑out, and validation.
Ability to create and manage design‑layout schedules that meet functional requirements and timelines.
Proficiency with Cadence Virtuoso (VXL), Mentor Graphics Calibre, or Synopsys IC Validator.
Strong understanding of CMOS fabrication, phase‑shift mask development, and multi‑patterning techniques.
Desired Skills
Experience developing memory‑cell models for simulation tools (e.g., Verilog‑A).
Experience with emerging memories such as MRAM, ReRAM, or PCM.
Experience building radiation‑tolerant layouts.
Published papers or patents related to memory‑design layout.
Additional Information
WD is committed to equal opportunity employment. We do not discriminate on the basis of race, color, ancestry, religion, sex, gender identity, age, national origin, sexual orientation, medical condition, marital status, disability, or any other legally protected characteristic. WD also provides accommodations for applicants with disabilities. For accommodation requests, contact jobs.accommodations@wdc.com.
Application deadline: June 30, 2026 . We may close recruitment earlier if the position is filled.
Compensation & Benefits
Salary will be based on education, experience, skills, performance, location, and business needs. The role is eligible for overtime and shift differentials where applicable.
Eligible for bonuses under WD’s STI Plan or SIP and for the LTI program (restricted stock units or cash equivalents) where suitable.
Comprehensive benefits include paid vacation, sick leave, medical/dental/vision coverage, life and disability insurance, flexible‑spending and health‑savings accounts, employee assistance program, tuition reimbursement, transit benefits, employee stock purchase plan, 401(k) plan, and a host of additional voluntary benefits.
Note: Pay and benefits are subject to company discretion and applicable law.
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Responsibilities
Develop high‑density memory chip custom layout, including shared operational circuitry and pitch‑line drivers; cover all design phases from architecture definition to tape‑out.
Run and debug physical‑verification flows (DRC, LVS, ERC, antenna checks); minimize parasitic R and C, address reliability issues (electromigration, IR‑drop, DFM robustness).
Coordinate split‑fab design and development between WD memory‑array layers and a CMOS foundry; harmonize wafer requirements, develop EDA tool design rules, and execute split‑fab tape‑out flow.
Qualifications
Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Physics, or a closely related field.
Proven experience in high‑density memory chip layout, tape‑out, and validation.
Ability to create and manage design‑layout schedules that meet functional requirements and timelines.
Proficiency with Cadence Virtuoso (VXL), Mentor Graphics Calibre, or Synopsys IC Validator.
Strong understanding of CMOS fabrication, phase‑shift mask development, and multi‑patterning techniques.
Desired Skills
Experience developing memory‑cell models for simulation tools (e.g., Verilog‑A).
Experience with emerging memories such as MRAM, ReRAM, or PCM.
Experience building radiation‑tolerant layouts.
Published papers or patents related to memory‑design layout.
Additional Information
WD is committed to equal opportunity employment. We do not discriminate on the basis of race, color, ancestry, religion, sex, gender identity, age, national origin, sexual orientation, medical condition, marital status, disability, or any other legally protected characteristic. WD also provides accommodations for applicants with disabilities. For accommodation requests, contact jobs.accommodations@wdc.com.
Application deadline: June 30, 2026 . We may close recruitment earlier if the position is filled.
Compensation & Benefits
Salary will be based on education, experience, skills, performance, location, and business needs. The role is eligible for overtime and shift differentials where applicable.
Eligible for bonuses under WD’s STI Plan or SIP and for the LTI program (restricted stock units or cash equivalents) where suitable.
Comprehensive benefits include paid vacation, sick leave, medical/dental/vision coverage, life and disability insurance, flexible‑spending and health‑savings accounts, employee assistance program, tuition reimbursement, transit benefits, employee stock purchase plan, 401(k) plan, and a host of additional voluntary benefits.
Note: Pay and benefits are subject to company discretion and applicable law.
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