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Radiation-Hardened Memory Chip Design Engineer

WD, San Jose, CA, United States


A technology company is seeking a full-time Research Staff Member in California. This role involves developing high-density memory chip layouts, requiring expertise in CMOS and proficiency with Cadence tools. The ideal candidate holds an advanced degree in Electrical Engineering or Physics and has experience in memory chip validation. The company values diverse opportunities and offers comprehensive benefits including medical coverage and a 401(k) plan. The application deadline is June 30, 2026, with potential early closure if filled.
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