Staff / Senior Staff Engineer, Physical Design
Renesas Electronics Corporation, Lincoln, NE, United States
Job Summary
Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.
Key Responsibilities
Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution
Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions
Qualifications
8+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs
Strong expertise in:
Timing closure and constraint management
Congestion analysis and resolution
Power integrity and power-aware physical implementation
Block and subsystem-level physical design flows
Solid understanding of SoC-level floorplanning and clocking methodologies, including:
Clock domain partitioning
Clock tree architecture
Skew management
Clock gating (Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)
Hands‑on experience with industry‑standard tools such as:
Synopsys ICC2, Fusion Compiler, PrimeTime
Cadence Innovus, Tempus, Certus
Signoff and analysis platforms
Proficiency in scripting and automation using Tcl, Python, and/or Perl
Deep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams
Strong understanding of low‑power design techniques and power‑aware implementation methodologies
Education
B.Tech or M.Tech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field
Equal Opportunity Statement
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
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Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.
Key Responsibilities
Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution
Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions
Qualifications
8+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs
Strong expertise in:
Timing closure and constraint management
Congestion analysis and resolution
Power integrity and power-aware physical implementation
Block and subsystem-level physical design flows
Solid understanding of SoC-level floorplanning and clocking methodologies, including:
Clock domain partitioning
Clock tree architecture
Skew management
Clock gating (Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)
Hands‑on experience with industry‑standard tools such as:
Synopsys ICC2, Fusion Compiler, PrimeTime
Cadence Innovus, Tempus, Certus
Signoff and analysis platforms
Proficiency in scripting and automation using Tcl, Python, and/or Perl
Deep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams
Strong understanding of low‑power design techniques and power‑aware implementation methodologies
Education
B.Tech or M.Tech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field
Equal Opportunity Statement
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
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