RTL Design Tech Lead (ASIC/SoC)
Bolt Graphics, Inc., Sunnyvale, CA, United States
Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
Our Values
Be Fearless : Unmute yourself. Test boundaries and get proven right.
Remain Adaptable : Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
Educate Your Ego : Selflessly collaborate towards our shared purpose.
About the role
We're looking for a seasoned RTL Design Tech Lead to drive micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines deep hands-on design expertise with technical leadership , guiding teams from architecture through tapeout.
The ideal candidate has strong ownership mindset, has led successful silicon bring-ups, and can operate effectively in both structured and fast-paced environments. This candidate must be willing to be an individual contributor, while leading others.
What you'll do
Own end-to-end RTL design for major subsystems or full-chip blocks
Define micro-architecture aligned with PPA (Power, Performance, Area) targets
Lead and mentor a team of RTL engineers (junior to senior ICs)
Drive design reviews, coding standards, and best practices
Collaborate closely with:
Physical Design (PD)
STA / Timing / DFT teams
Ensure high RTL quality via:
Low-power (UPF) compliance
Debug complex issues across:
RTL simulation
Gate-Level Simulation (GLS)
Work with foundry and backend constraints (timing, congestion, IR, etc.)
Drive schedule, risk mitigation, and execution toward tapeout
Required Qualifications
Bachelor’s or Master’s in Electrical / Computer Engineering
10+ years of experience in ASIC/SoC RTL design
Strong understanding of:
Timing (setup/hold, STA correlation)
CDC/RDC methodologies
Reset strategies and clocking architectures
Proven experience leading blocks through multiple tapeouts
Hands-on experience with synthesis (e.g., Design Compiler)
Strong debugging and problem-solving ability
Excellent communication across cross-functional teams
Ownership and accountability for silicon success
Ability to operate under tight tapeout schedules
Preferred Qualifications
Experience in advanced nodes (e.g., 12FFC, 7nm, 5nm)
Strong GLS expertise (SDF, X-propagation, power-aware sims)
Knowledge of DFT (scan, MBIST, compression)
Experience with high-speed IPs (DDR, PCIe, SerDes) or memory subsystems
Prior collaboration with foundries such as TSMC
Experience in startup environments or first-silicon efforts
Exposure to packaging (flip-chip, bump planning, IO constraints)
Experience with low-frequency testchips or rapid prototyping
Government clearance is preferred
As an IC, you will provide technical direction and architectural clarity
Mentor and grow team members
Drive high engineering standards and design quality
Balance hands-on work with leadership responsibilities
Compensation Range
$220,000–$250,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.
Medical, Dental, & Vision - 100% covered premiums
Equity - Stock Options
401(k) match
Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.
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Our Values
Be Fearless : Unmute yourself. Test boundaries and get proven right.
Remain Adaptable : Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
Educate Your Ego : Selflessly collaborate towards our shared purpose.
About the role
We're looking for a seasoned RTL Design Tech Lead to drive micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines deep hands-on design expertise with technical leadership , guiding teams from architecture through tapeout.
The ideal candidate has strong ownership mindset, has led successful silicon bring-ups, and can operate effectively in both structured and fast-paced environments. This candidate must be willing to be an individual contributor, while leading others.
What you'll do
Own end-to-end RTL design for major subsystems or full-chip blocks
Define micro-architecture aligned with PPA (Power, Performance, Area) targets
Lead and mentor a team of RTL engineers (junior to senior ICs)
Drive design reviews, coding standards, and best practices
Collaborate closely with:
Physical Design (PD)
STA / Timing / DFT teams
Ensure high RTL quality via:
Low-power (UPF) compliance
Debug complex issues across:
RTL simulation
Gate-Level Simulation (GLS)
Work with foundry and backend constraints (timing, congestion, IR, etc.)
Drive schedule, risk mitigation, and execution toward tapeout
Required Qualifications
Bachelor’s or Master’s in Electrical / Computer Engineering
10+ years of experience in ASIC/SoC RTL design
Strong understanding of:
Timing (setup/hold, STA correlation)
CDC/RDC methodologies
Reset strategies and clocking architectures
Proven experience leading blocks through multiple tapeouts
Hands-on experience with synthesis (e.g., Design Compiler)
Strong debugging and problem-solving ability
Excellent communication across cross-functional teams
Ownership and accountability for silicon success
Ability to operate under tight tapeout schedules
Preferred Qualifications
Experience in advanced nodes (e.g., 12FFC, 7nm, 5nm)
Strong GLS expertise (SDF, X-propagation, power-aware sims)
Knowledge of DFT (scan, MBIST, compression)
Experience with high-speed IPs (DDR, PCIe, SerDes) or memory subsystems
Prior collaboration with foundries such as TSMC
Experience in startup environments or first-silicon efforts
Exposure to packaging (flip-chip, bump planning, IO constraints)
Experience with low-frequency testchips or rapid prototyping
Government clearance is preferred
As an IC, you will provide technical direction and architectural clarity
Mentor and grow team members
Drive high engineering standards and design quality
Balance hands-on work with leadership responsibilities
Compensation Range
$220,000–$250,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.
Medical, Dental, & Vision - 100% covered premiums
Equity - Stock Options
401(k) match
Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.
#J-18808-Ljbffr