Principal Design Verification Engineer
Bolt Graphics, Inc., Sunnyvale, CA, United States
Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
Our Values
Be Fearless : Unmute yourself. Test boundaries and get proven right.
Remain Adaptable : Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
Educate Your Ego : Selflessly collaborate towards our shared purpose.
About the role:
As a Principal Design Verification Engineer , you will own the verification strategy and execution for complex IPs or full‑chip SoC. You will lead a team of verification engineers, define methodologies, drive coverage closure, and ensure high‑quality silicon delivery.
What you'll do:
Build, mentor, and scale ahigh‑performing DV team
Establishverification plans, milestones, and coverage goals
Drive alignment acrossarchitecture, RTL, and physical design teams
Verification Execution
Lead development ofUVM‑based verification environments
Define testbench architecture, stimulus strategy, and reusable components
Drive functional, code, and assertion coverage closure
Oversee regression infrastructure, debug, and signoff criteria
Advanced Verification & Signoff
Drive GLS (Gate‑Level Simulation) with SDF annotation and timing‑aware debug
Manage low‑power verification (UPF/CPF) and power‑aware simulation
Oversee formal verification, linting, CDC/RDC analysis
Ensure robust reset, clocking, and cross‑domain verification
Cross‑Functional Collaboration
Work with RTL teams on design‑for‑verification (DFV) improvements
Collaborate with PD teams on timing‑related verification issues
Support post‑silicon bring‑up and debug
Interface with customers/partners on verification readiness and quality
Required Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering or related field
12–15 years of experience in ASIC/SoC design verification
Proven experience leading verification teams and delivering multiple tapeouts
Strong expertise in:
SystemVerilog and UVM methodology
Functional coverage, assertions (SVA), and constrained‑random verification
Debugging complex SoC‑level issues
Hands‑on experience with industry‑standard tools such as:
Synopsys VCS/Cadence Xcelium
Strong understanding of:
Gate‑level simulation and SDF annotation
Excellent leadership, communication, and problem‑solving skills
Preferred Qualifications:
Experience in CPU/GPU/AI/Networking SoCs
Expertise in GLS debug (X‑propagation, SDF issues, timing failures)
Familiarity with emulation platforms (e.g., Synopsys ZeBu)
Experience with post‑silicon validation and bring‑up
Knowledge of performance verification and system‑level validation
Strong scripting skills (Python/TCL) for automation and regression scaling
Compensation Range: $250,000–$280,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.
Medical, Dental, & Vision - 100% covered premiums
Equity - Stock Options
401(k) match
Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.
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Our Values
Be Fearless : Unmute yourself. Test boundaries and get proven right.
Remain Adaptable : Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
Educate Your Ego : Selflessly collaborate towards our shared purpose.
About the role:
As a Principal Design Verification Engineer , you will own the verification strategy and execution for complex IPs or full‑chip SoC. You will lead a team of verification engineers, define methodologies, drive coverage closure, and ensure high‑quality silicon delivery.
What you'll do:
Build, mentor, and scale ahigh‑performing DV team
Establishverification plans, milestones, and coverage goals
Drive alignment acrossarchitecture, RTL, and physical design teams
Verification Execution
Lead development ofUVM‑based verification environments
Define testbench architecture, stimulus strategy, and reusable components
Drive functional, code, and assertion coverage closure
Oversee regression infrastructure, debug, and signoff criteria
Advanced Verification & Signoff
Drive GLS (Gate‑Level Simulation) with SDF annotation and timing‑aware debug
Manage low‑power verification (UPF/CPF) and power‑aware simulation
Oversee formal verification, linting, CDC/RDC analysis
Ensure robust reset, clocking, and cross‑domain verification
Cross‑Functional Collaboration
Work with RTL teams on design‑for‑verification (DFV) improvements
Collaborate with PD teams on timing‑related verification issues
Support post‑silicon bring‑up and debug
Interface with customers/partners on verification readiness and quality
Required Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering or related field
12–15 years of experience in ASIC/SoC design verification
Proven experience leading verification teams and delivering multiple tapeouts
Strong expertise in:
SystemVerilog and UVM methodology
Functional coverage, assertions (SVA), and constrained‑random verification
Debugging complex SoC‑level issues
Hands‑on experience with industry‑standard tools such as:
Synopsys VCS/Cadence Xcelium
Strong understanding of:
Gate‑level simulation and SDF annotation
Excellent leadership, communication, and problem‑solving skills
Preferred Qualifications:
Experience in CPU/GPU/AI/Networking SoCs
Expertise in GLS debug (X‑propagation, SDF issues, timing failures)
Familiarity with emulation platforms (e.g., Synopsys ZeBu)
Experience with post‑silicon validation and bring‑up
Knowledge of performance verification and system‑level validation
Strong scripting skills (Python/TCL) for automation and regression scaling
Compensation Range: $250,000–$280,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.
Medical, Dental, & Vision - 100% covered premiums
Equity - Stock Options
401(k) match
Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.
#J-18808-Ljbffr